Thermally Oxidized InAlN of Different Compositions for InAlN/GaN Heterostructure Field-Effect Transistors
Identifieur interne : 001347 ( Main/Repository ); précédent : 001346; suivant : 001348Thermally Oxidized InAlN of Different Compositions for InAlN/GaN Heterostructure Field-Effect Transistors
Auteurs : RBID : Pascal:13-0026913Descripteurs français
- Pascal (Inist)
- Semiconducteur III-V, Composé III-V, Hétérostructure, Transistor effet champ, Couche barrière, Courant drain, Mesure capacité électrique, Mesure charge électrique, Densité charge, Distribution charge électronique, Epaisseur, Capacité électrique, Electrode commande, Courant impulsionnel, Nitrure de gallium, Nitrure d'indium, Tellurure de gallium, Nitrure de silicium, Densité élevée, Densité état, Piège, Transistor effet champ hétérojonction, Oxydation, Etat défaut, GaN, InN, Substrat GaN, SiNx, 8105E, 8530T.
English descriptors
- KwdEn :
- Barrier layer, Capacitance, Capacitance measurement, Charge density, Charge measurement, Defect states, Density of states, Drain current, Electron charge distribution, Field effect transistors, Gallium nitride, Gallium tellurides, Gates, Heterojunction field effect transistor, Heterostructures, High density, III-V compound, III-V semiconductors, Indium nitride, Oxidation, Pulse current, Silicon nitride, Thickness, Traps.
Abstract
Properties of InAlN/GaN heterostructure field-effect transistors with thermally oxidized (750°C, 2 min) InAlN barrier layers of different compositions (InN = 13%, 17%, and 21%) were evaluated. The saturation drain current was inversely proportional to the InN content and was lower than that obtained with nonoxidized devices. From the capacitance measurement, the resulting sheet charge density decreased from 1.1 x 1013 cm-2 to 0.6 x 1013 cm-2 with increased InN content, and it was only approximately 50% of that of the nonoxidized counterparts. The oxide thickness of approximately 1 nm was extracted from the zero-bias capacitances. The pulsed measurements yielded a very high gate lag independent from the InAlN composition (the pulsed-to-static drain current ratio was ∼0.5 for a 200-ns pulse width). On the other hand, a significantly lower gate lag was observed on nonoxidized SiNx passivated InAIN/GaN devices. The results demonstrate that a high density of trap states was created in the thermally oxidized InAIN/GaN structures.
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<record><TEI><teiHeader><fileDesc><titleStmt><title xml:lang="en" level="a">Thermally Oxidized InAlN of Different Compositions for InAlN/GaN Heterostructure Field-Effect Transistors</title><author><name sortKey="Kordos, P" uniqKey="Kordos P">P. Kordos</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Department of Microelectronics, Slovak University of Technology</s1><s2>81219 Bratislava</s2><s3>SVK</s3><sZ>1 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ></inist:fA14><country>Slovaquie</country><wicri:noRegion>81219 Bratislava</wicri:noRegion></affiliation><affiliation wicri:level="1"><inist:fA14 i1="02"><s1>Institute of Electrical Engineering, Slovak Academy of Sciences</s1><s2>84104 Bratislava</s2><s3>SVK</s3><sZ>1 aut.</sZ></inist:fA14><country>Slovaquie</country><wicri:noRegion>84104 Bratislava</wicri:noRegion></affiliation></author><author><name sortKey="Mikulics, M" uniqKey="Mikulics M">M. Mikulics</name><affiliation wicri:level="1"><inist:fA14 i1="03"><s1>Research Centre Jülich</s1><s2>52435 Jülich</s2><s3>DEU</s3><sZ>2 aut.</sZ><sZ>6 aut.</sZ></inist:fA14><country>Allemagne</country><wicri:noRegion>52435 Jülich</wicri:noRegion><wicri:noRegion>Research Centre Jülich</wicri:noRegion><wicri:noRegion>Research Centre Jülich</wicri:noRegion></affiliation></author><author><name sortKey="Stoklas, R" uniqKey="Stoklas R">R. Stoklas</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Department of Microelectronics, Slovak University of Technology</s1><s2>81219 Bratislava</s2><s3>SVK</s3><sZ>1 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ></inist:fA14><country>Slovaquie</country><wicri:noRegion>81219 Bratislava</wicri:noRegion></affiliation></author><author><name sortKey="Cico, K" uniqKey="Cico K">K. Cico</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Department of Microelectronics, Slovak University of Technology</s1><s2>81219 Bratislava</s2><s3>SVK</s3><sZ>1 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ></inist:fA14><country>Slovaquie</country><wicri:noRegion>81219 Bratislava</wicri:noRegion></affiliation></author><author><name sortKey="Dadgar, A" uniqKey="Dadgar A">A. Dadgar</name><affiliation wicri:level="1"><inist:fA14 i1="04"><s1>Institute of Experimental Physics, University Magdeburg</s1><s2>39016 Magdeburg</s2><s3>DEU</s3><sZ>5 aut.</sZ><sZ>7 aut.</sZ></inist:fA14><country>Allemagne</country><wicri:noRegion>39016 Magdeburg</wicri:noRegion><wicri:noRegion>University Magdeburg</wicri:noRegion><wicri:noRegion>39016 Magdeburg</wicri:noRegion></affiliation></author><author><name sortKey="Grutzmacher, D" uniqKey="Grutzmacher D">D. Grutzmacher</name><affiliation wicri:level="1"><inist:fA14 i1="03"><s1>Research Centre Jülich</s1><s2>52435 Jülich</s2><s3>DEU</s3><sZ>2 aut.</sZ><sZ>6 aut.</sZ></inist:fA14><country>Allemagne</country><wicri:noRegion>52435 Jülich</wicri:noRegion><wicri:noRegion>Research Centre Jülich</wicri:noRegion><wicri:noRegion>Research Centre Jülich</wicri:noRegion></affiliation></author><author><name sortKey="Krost, A" uniqKey="Krost A">A. Krost</name><affiliation wicri:level="1"><inist:fA14 i1="04"><s1>Institute of Experimental Physics, University Magdeburg</s1><s2>39016 Magdeburg</s2><s3>DEU</s3><sZ>5 aut.</sZ><sZ>7 aut.</sZ></inist:fA14><country>Allemagne</country><wicri:noRegion>39016 Magdeburg</wicri:noRegion><wicri:noRegion>University Magdeburg</wicri:noRegion><wicri:noRegion>39016 Magdeburg</wicri:noRegion></affiliation></author></titleStmt><publicationStmt><idno type="inist">13-0026913</idno><date when="2012">2012</date><idno type="stanalyst">PASCAL 13-0026913 INIST</idno><idno type="RBID">Pascal:13-0026913</idno><idno type="wicri:Area/Main/Corpus">001435</idno><idno type="wicri:Area/Main/Repository">001347</idno></publicationStmt><seriesStmt><idno type="ISSN">0361-5235</idno><title level="j" type="abbreviated">J. electron. mater.</title><title level="j" type="main">Journal of electronic materials</title></seriesStmt></fileDesc><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Barrier layer</term><term>Capacitance</term><term>Capacitance measurement</term><term>Charge density</term><term>Charge measurement</term><term>Defect states</term><term>Density of states</term><term>Drain current</term><term>Electron charge distribution</term><term>Field effect transistors</term><term>Gallium nitride</term><term>Gallium tellurides</term><term>Gates</term><term>Heterojunction field effect transistor</term><term>Heterostructures</term><term>High density</term><term>III-V compound</term><term>III-V semiconductors</term><term>Indium nitride</term><term>Oxidation</term><term>Pulse current</term><term>Silicon nitride</term><term>Thickness</term><term>Traps</term></keywords><keywords scheme="Pascal" xml:lang="fr"><term>Semiconducteur III-V</term><term>Composé III-V</term><term>Hétérostructure</term><term>Transistor effet champ</term><term>Couche barrière</term><term>Courant drain</term><term>Mesure capacité électrique</term><term>Mesure charge électrique</term><term>Densité charge</term><term>Distribution charge électronique</term><term>Epaisseur</term><term>Capacité électrique</term><term>Electrode commande</term><term>Courant impulsionnel</term><term>Nitrure de gallium</term><term>Nitrure d'indium</term><term>Tellurure de gallium</term><term>Nitrure de silicium</term><term>Densité élevée</term><term>Densité état</term><term>Piège</term><term>Transistor effet champ hétérojonction</term><term>Oxydation</term><term>Etat défaut</term><term>GaN</term><term>InN</term><term>Substrat GaN</term><term>SiNx</term><term>8105E</term><term>8530T</term></keywords></textClass></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">Properties of InAlN/GaN heterostructure field-effect transistors with thermally oxidized (750°C, 2 min) InAlN barrier layers of different compositions (InN = 13%, 17%, and 21%) were evaluated. The saturation drain current was inversely proportional to the InN content and was lower than that obtained with nonoxidized devices. From the capacitance measurement, the resulting sheet charge density decreased from 1.1 x 10<sup>13</sup> cm<sup>-2</sup> to 0.6 x 10<sup>13</sup> cm<sup>-2</sup> with increased InN content, and it was only approximately 50% of that of the nonoxidized counterparts. The oxide thickness of approximately 1 nm was extracted from the zero-bias capacitances. The pulsed measurements yielded a very high gate lag independent from the InAlN composition (the pulsed-to-static drain current ratio was ∼0.5 for a 200-ns pulse width). On the other hand, a significantly lower gate lag was observed on nonoxidized SiN<sub>x</sub> passivated InAIN/GaN devices. The results demonstrate that a high density of trap states was created in the thermally oxidized InAIN/GaN structures.</div></front></TEI><inist><standard h6="B"><pA><fA01 i1="01" i2="1"><s0>0361-5235</s0></fA01><fA02 i1="01"><s0>JECMA5</s0></fA02><fA03 i2="1"><s0>J. electron. mater.</s0></fA03><fA05><s2>41</s2></fA05><fA06><s2>11</s2></fA06><fA08 i1="01" i2="1" l="ENG"><s1>Thermally Oxidized InAlN of Different Compositions for InAlN/GaN Heterostructure Field-Effect Transistors</s1></fA08><fA11 i1="01" i2="1"><s1>KORDOS (P.)</s1></fA11><fA11 i1="02" i2="1"><s1>MIKULICS (M.)</s1></fA11><fA11 i1="03" i2="1"><s1>STOKLAS (R.)</s1></fA11><fA11 i1="04" i2="1"><s1>CICO (K.)</s1></fA11><fA11 i1="05" i2="1"><s1>DADGAR (A.)</s1></fA11><fA11 i1="06" i2="1"><s1>GRUTZMACHER (D.)</s1></fA11><fA11 i1="07" i2="1"><s1>KROST (A.)</s1></fA11><fA14 i1="01"><s1>Department of Microelectronics, Slovak University of Technology</s1><s2>81219 Bratislava</s2><s3>SVK</s3><sZ>1 aut.</sZ><sZ>3 aut.</sZ><sZ>4 aut.</sZ></fA14><fA14 i1="02"><s1>Institute of Electrical Engineering, Slovak Academy of Sciences</s1><s2>84104 Bratislava</s2><s3>SVK</s3><sZ>1 aut.</sZ></fA14><fA14 i1="03"><s1>Research Centre Jülich</s1><s2>52435 Jülich</s2><s3>DEU</s3><sZ>2 aut.</sZ><sZ>6 aut.</sZ></fA14><fA14 i1="04"><s1>Institute of Experimental Physics, University Magdeburg</s1><s2>39016 Magdeburg</s2><s3>DEU</s3><sZ>5 aut.</sZ><sZ>7 aut.</sZ></fA14><fA20><s1>3013-3016</s1></fA20><fA21><s1>2012</s1></fA21><fA23 i1="01"><s0>ENG</s0></fA23><fA43 i1="01"><s1>INIST</s1><s2>15479</s2><s5>354000505438430040</s5></fA43><fA44><s0>0000</s0><s1>© 2013 INIST-CNRS. All rights reserved.</s1></fA44><fA45><s0>14 ref.</s0></fA45><fA47 i1="01" i2="1"><s0>13-0026913</s0></fA47><fA60><s1>P</s1></fA60><fA61><s0>A</s0></fA61><fA64 i1="01" i2="1"><s0>Journal of electronic materials</s0></fA64><fA66 i1="01"><s0>DEU</s0></fA66><fC01 i1="01" l="ENG"><s0>Properties of InAlN/GaN heterostructure field-effect transistors with thermally oxidized (750°C, 2 min) InAlN barrier layers of different compositions (InN = 13%, 17%, and 21%) were evaluated. The saturation drain current was inversely proportional to the InN content and was lower than that obtained with nonoxidized devices. From the capacitance measurement, the resulting sheet charge density decreased from 1.1 x 10<sup>13</sup> cm<sup>-2</sup> to 0.6 x 10<sup>13</sup> cm<sup>-2</sup> with increased InN content, and it was only approximately 50% of that of the nonoxidized counterparts. The oxide thickness of approximately 1 nm was extracted from the zero-bias capacitances. The pulsed measurements yielded a very high gate lag independent from the InAlN composition (the pulsed-to-static drain current ratio was ∼0.5 for a 200-ns pulse width). On the other hand, a significantly lower gate lag was observed on nonoxidized SiN<sub>x</sub> passivated InAIN/GaN devices. The results demonstrate that a high density of trap states was created in the thermally oxidized InAIN/GaN structures.</s0></fC01><fC02 i1="01" i2="3"><s0>001B80A05H</s0></fC02><fC02 i1="02" i2="X"><s0>001D03F04</s0></fC02><fC02 i1="03" i2="X"><s0>001D03C</s0></fC02><fC03 i1="01" i2="3" l="FRE"><s0>Semiconducteur III-V</s0><s5>01</s5></fC03><fC03 i1="01" i2="3" l="ENG"><s0>III-V semiconductors</s0><s5>01</s5></fC03><fC03 i1="02" i2="X" l="FRE"><s0>Composé III-V</s0><s5>02</s5></fC03><fC03 i1="02" i2="X" l="ENG"><s0>III-V compound</s0><s5>02</s5></fC03><fC03 i1="02" i2="X" l="SPA"><s0>Compuesto III-V</s0><s5>02</s5></fC03><fC03 i1="03" i2="3" l="FRE"><s0>Hétérostructure</s0><s5>03</s5></fC03><fC03 i1="03" i2="3" l="ENG"><s0>Heterostructures</s0><s5>03</s5></fC03><fC03 i1="04" i2="3" l="FRE"><s0>Transistor effet champ</s0><s5>04</s5></fC03><fC03 i1="04" i2="3" l="ENG"><s0>Field effect transistors</s0><s5>04</s5></fC03><fC03 i1="05" i2="3" l="FRE"><s0>Couche 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l="ENG"><s0>Traps</s0><s5>31</s5></fC03><fC03 i1="22" i2="X" l="FRE"><s0>Transistor effet champ hétérojonction</s0><s5>32</s5></fC03><fC03 i1="22" i2="X" l="ENG"><s0>Heterojunction field effect transistor</s0><s5>32</s5></fC03><fC03 i1="22" i2="X" l="SPA"><s0>Transistor efecto campo heterounión</s0><s5>32</s5></fC03><fC03 i1="23" i2="3" l="FRE"><s0>Oxydation</s0><s5>33</s5></fC03><fC03 i1="23" i2="3" l="ENG"><s0>Oxidation</s0><s5>33</s5></fC03><fC03 i1="24" i2="3" l="FRE"><s0>Etat défaut</s0><s5>34</s5></fC03><fC03 i1="24" i2="3" l="ENG"><s0>Defect states</s0><s5>34</s5></fC03><fC03 i1="25" i2="3" l="FRE"><s0>GaN</s0><s4>INC</s4><s5>46</s5></fC03><fC03 i1="26" i2="3" l="FRE"><s0>InN</s0><s4>INC</s4><s5>47</s5></fC03><fC03 i1="27" i2="3" l="FRE"><s0>Substrat GaN</s0><s4>INC</s4><s5>48</s5></fC03><fC03 i1="28" i2="3" l="FRE"><s0>SiNx</s0><s4>INC</s4><s5>49</s5></fC03><fC03 i1="29" i2="3" l="FRE"><s0>8105E</s0><s4>INC</s4><s5>65</s5></fC03><fC03 i1="30" i2="3" l="FRE"><s0>8530T</s0><s4>INC</s4><s5>71</s5></fC03><fN21><s1>014</s1></fN21></pA></standard></inist></record>Pour manipuler ce document sous Unix (Dilib)
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